Stacked semiconductor dies with selective capillary under fill

ABSTRACT

Stacked semiconductor dies are provided with selective capillary under fill to avoid wafer warpage during curing. In one embodiment, a method of manufacturing a semiconductor device includes forming at least three stacks of semiconductor dies over a substrate, the stacks spaced apart from one another by gaps. A first sealing material such as a capillary under fill material is deposited into a first subset of the gaps. A second sealing material such as a mold resin is deposited into a second subset of the gaps. The first and second sealing materials are cured, and the die stacks are then singulated.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.15/901,799, filed Feb. 21, 2018; which is a divisional of U.S.application Ser. No. 14/982,196, filed Dec. 29, 2015, now U.S. Pat. No.9,935,082; each of which is incorporated herein by reference in itsentirety.

TECHNICAL FIELD

The disclosed embodiments relate to semiconductor devices and moreparticularly to wafer-level processing of semiconductor devices.

BACKGROUND

Electronic products require semiconductor devices to have an extremelyhigh density of components in a very limited space. For example, thespace available for memory devices, imagers, processors, displays, andother microelectronic components is quite limited in cell phones, PDAs,portable computers, and many other products. As such, there is a strongdrive to reduce the surface area or “footprint” of the device on aprinted circuit board or other mounting surface. One technique used toincrease the density of semiconductor dies within a given footprint isto stack one semiconductor die on top of another.

Stacked semiconductor devices are often manufactured on semiconductorworkpieces or other types of workpieces. In a typical application,several stacks of dies (e.g., devices) are fabricated on a singleworkpiece using sophisticated and expensive equipment and processes. Theindividual stacks of dies are then separated by dicing or otherwisesingulating the stacks from the wafer. The gaps between adjacent stackeddies are often filled using a capillary under fill (CUF) material thatis cured before singulating the stacked dies from the wafer. In manycases, curing the CUF material results in wafer warpage, therebyimpairing singulation and subsequent processing of the stacked dies.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1H are top plan and cross-sectional views of an assemblycomprising a wafer having a plurality of stacks of semiconductor diesthereon at various stages of processing in accordance with an embodimentof the present technology.

FIG. 2A is a top plan view of a portion of the assembly of FIG. 1Hbefore singulating the stacks of semiconductor dies.

FIG. 2B is a cross-sectional view of the portion of the assembly of FIG.2A taken along line B-B.

FIG. 2C is a cross-sectional view of the portion of the assembly of FIG.2A taken along line C-C.

FIGS. 3A-3D are cross-sectional views of an assembly comprising a waferhaving a plurality of stacks of semiconductor dies thereon at variousstages of processing in accordance with another embodiment of thepresent technology.

FIG. 4A is a top plan view of a portion of the assembly of FIG. 3D aftersingulating the stacks of semiconductor dies.

FIG. 4B is a cross-sectional view of the portion of the assembly of FIG.4A taken along line B-B.

FIG. 4C is a cross-sectional view of the portion of the assembly of FIG.4A taken along line C-C.

FIG. 5 is a cross-sectional view of a larger device assemblyincorporating a singulated stack of dies therein.

FIG. 6 is a schematic view of a system that includes a stackedsemiconductor die assembly configured in accordance with embodiments ofthe present technology.

DETAILED DESCRIPTION

Specific details of several embodiments of stacked semiconductor dieshaving one or more sides at least partially covered with a first sealingmaterial and other sides covered with a second sealing are describedbelow along with associated systems and methods therefor. The term“semiconductor die” generally refers to a die having integrated circuitsor components, data storage elements, processing components, and/orother features manufactured on semiconductor substrates. For example,semiconductor dies can include integrated circuit memory and/or logiccircuitry. A person skilled in the relevant art will also understandthat the technology may have additional embodiments, and that thetechnology may be practiced without several of the details of theembodiments described below with reference to FIGS. 1A-6.

As used herein, the terms “vertical,” “lateral,” “upper,” and “lower”can refer to relative directions or positions of features in thesemiconductor die assemblies in view of the orientation shown in theFigures. For example, “upper” or “uppermost” can refer to a featurepositioned closer to the top of a page than another feature. Theseterms, however, should be construed broadly to include semiconductordevices having other orientations, such as inverted or inclinedorientations where top/bottom, over/under, above/below, up/down andleft/right can be interchanged depending on the orientation.

FIGS. 1A-1H are top plan and cross-sectional views of an assembly 100comprising a wafer 101 having a plurality of stacks 103 (identifiedindividually as 103 a-h in FIG. 1B) of semiconductor dies thereon atvarious stages of processing in accordance with an embodiment of thepresent technology. FIG. 1A is a top plan view of the assembly 100, andFIG. 1B is a cross-sectional view of the assembly 100 taken along lineB-B in FIG. 1A. Referring to FIGS. 1A and 1B together, the stacks 103are arranged in an array across the upper surface 105 of the wafer 101.The wafer 101 can be, for example, a silicon wafer. In the illustratedembodiment, the array can have multiple rows with each row having eightstacks 103 a-h across the surface of the wafer 101, however in otherembodiments the number of stacks 103 can vary. The wafer 101 is disposedover and supported by a support substrate 107. The support substrate 107is thicker than the wafer 101 and provides structural support andrigidity to the wafer 101 during processing.

In the illustrated embodiment, each individual stack 103 includes foursemiconductor dies 109 a-d stacked vertically on top of one another. Insome embodiments, the semiconductor dies 109 a-d can include memorychips, interface chips, or other types of chips. The illustratedsemiconductor dies 109 a-d have substantially identical dimensions,however in other embodiments the individual dies 109 a-d can vary fromeach other in footprint, thickness, shape, or other dimensions. The foursemiconductor dies 109 a-d are stacked over a logic circuit 111 which isformed in or on the wafer 101 and the logic circuit 111 is in electricalcommunication with the semiconductor dies 109 a-d using, for example,the through-silicon vias (TSVs) 113 that extend through thesemiconductor dies 109 a-d. In other embodiments various other types ofinterconnects can be used. Although the stacks 103 shown in FIG. 1B eachinclude four semiconductor dies 109 a-d, in other embodiments there maybe fewer or greater numbers of semiconductor dies, for example two totwelve and any integer thereof, or more semiconductor dies can bestacked over one another.

In the illustrated embodiment, each stack 103 defines a substantiallyrectangular geometric prism having side surfaces 115 a-d (FIG. 1A), alower surface 117 (FIG. 1B) adjacent to the logic circuit 111, and anupper surface 119 (FIG. 1B) opposite the lower surface 117. Adjacentstacks 103 are laterally separated from one another by a plurality ofgaps 121 a-g (collectively “gaps 121”); for example the first stack 103a is separated from the second stack 103 b by the first gap 121 a.Although the gaps 121 a-g are illustrated in one cross-sectionaldimension, similar gaps separate each stack 103 n from adjacent stacksin the perpendicular direction (i.e., gaps separating each stack 103from stacks in adjacent rows).

FIG. 1C is a cross-sectional view of the assembly 100 after a firstsealing material 123 has been dispensed into a subset of the gaps 121between adjacent stacks 103. The first sealing material 123 can be, forexample, a capillary under fill (CUF) material dispensed from acapillary. FIG. 1D is a top plan view of a portion of the assembly 100in which the first sealing material 123 is dispensed along lines 125 andis not dispensed along lines 127. Arrows 129 (FIG. 1) indicate thedirection of flow of the first sealing material 123 from the dispenser.Referring to FIGS. 1C and 1D together, the movement of the dispenser todeposit the first sealing material 123 along lines 125 results in firstsealing material 123 filling in the space between individualsemiconductor dies 109 a-d in each of the stacks 103, as well as fillingin the gaps 121 into which the first sealing material is dispensed. Inthe illustrated embodiment, the dispenser deposits the first sealingmaterial 123 into a first subset of the gaps 121 including gaps 121 a,121 c, 121 e, and 121 g, but not in a second subset of the gaps 121including gaps 121 b, 121 d, and 121 f.

FIG. 1E is a cross-sectional view of the assembly 100 after a secondsealing material 131 is deposited over the stacks 103 and the uppersurface 105 of the wafer 101. The second sealing material 131 can be,for example, a mold resin material. The second sealing material 131covers the upper surfaces 119 of the stacks 103 and fills in the secondsubset of gaps 121 in which the first sealing material 123 is notalready present. In the illustrated embodiment, the second sealingmaterial 131 fills in the gaps 121 b, 121 d, and 121 f, as well as theremaining side surfaces of the stacks 103. The assembly 100 can then beannealed to cure the first and second sealing materials 123 and 131.

The first sealing material 123 and the second sealing material 131 canhave different properties to achieve desired results. For example, thefirst sealing material 123 can have a lower filler concentration of afiller material (e.g., filler containing ratio) and/or a lower viscositythan the second sealing material 131. Furthermore, the first sealingmaterial 123 can have a greater linear coefficient of thermal expansion(CTE) and/or a greater thermal cure shrinkage coefficient than thesecond sealing material 131. In some embodiments, the first sealingmaterial 123 can be a CUF material and the second sealing material 131can be a mold resin material. In conventional chip-on-wafer processes,CUF material is dispensed along both lines 125 and 127 (FIG. 1D),thereby filling in all the gaps between adjacent stacks. However, due tothe material properties of the CUF material (e.g., low viscosity and lowfiller containing ratio), during subsequent annealing the curing of theCUF material can cause wafer warpage. Mold resin material, due to itsdistinct material properties (e.g., higher viscosity and higher fillercontaining ratio), is not as susceptible to causing wafer warpage duringthe curing process. Accordingly, by reducing the total amount of thefirst sealing material—such as a CUF material—provided in between thestacks of dies, wafer warpage caused by the curing process can bereduced.

FIG. 1F is a cross-sectional view of the assembly 100 after backgrindingand planarization. For example, an upper portion of the assembly 100shown in FIG. 1E can be removed by backgrinding followed bychemical-mechanical planarization (CMP) or another removal technique toform an upper surface 133 along the remaining second sealing material131 that is substantially coplanar with the upper surfaces 119 of eachof the stacks 103. In some embodiments, a portion of the uppermostsemiconductor die 109 a in each stack 103 can be removed duringbackgrinding and CMP.

FIG. 1G is a cross-sectional view of the assembly 100 after removal ofthe support substrate 107 and singulation of some of the stacks 103.FIG. 1H is a top plan view of a portion of the assembly 100 aftersingulation of the stacks 103. Referring to FIGS. 1G and 1H together,the support substrate 107 is removed from the wafer 101 and placed on atape (not shown) and then a wafer saw or other technique is used to dicethe wafer 101 along the gaps 121 as indicated by lines 135 to singulatethe individual stacks 103. The stacks 103 can then be separately mountedinto other assemblies as described in more detail below.

FIG. 2A is a top plan view of a portion of the assembly 100 of FIG. 1Hbefore singulating the stacked semiconductor dies. Four individualstacks 103 i-l are arranged in an array over the wafer 101. The firstsealing material 123 is disposed in the gap 121 h that separates theleft stacks 103 i and 103 j from the right stacks 103 k and 103 l. Thesecond sealing material 131 is disposed in the gap 121 i that separatesthe upper stacks 103 i and 103 k from the lower stacks 103 j and 103 l,and further surrounds the remaining sides of the stacks 103 i-l. Theassembly 100 is diced to singulate the stacks 103 i-l, including dicingalong the gaps 121 h and 121 i. FIG. 2B is a cross-sectional view of theportion of the assembly 100 of FIG. 2A taken along line B-B aftersingulating the stacks 103, and FIG. 2C is a cross-sectional view of theportion of the assembly 100 of FIG. 2A taken along line C-C aftersingulating the stacks 103. Referring to FIGS. 2B and 2C together, aftersingulation each of the stacks 103 i-l has four sides. Of the foursides, the first sealing material 123 is disposed over one of the sidesand the second sealing material 131 is disposed over the remaining threeof the four sides. In particular, the side of each of the stacks 103 i-hthat faces towards the gap 121 h is, after singulation, covered by thefirst sealing material 123. The first sealing material 123 also fills inthe areas between individual semiconductor dies 109 of the individualstacks 103.

The particular configuration of the stacks 103 i-l can reduce the riskof wafer warpage during the curing process. As noted above, each of thestacks 103 i-l has one side covered with the first sealing material 123and the remaining three sides covered with the second sealing material131. The first sealing material 123 can have material properties thatcontribute more to wafer warpage than the second sealing material 131.For example, the first sealing material 123 can have a lower fillercontaining ratio, a lower viscosity, a greater linear coefficient ofthermal expansion, and/or a greater thermal cure shrinkage coefficientthan the second sealing material 131. Accordingly, by covering only oneside of the stacks 103 i-l with the first sealing material 123 and thecovering the remaining three sides with the second sealing material 131,the overall amount of the first sealing material 123 is reduced andthere is correspondingly a lower likelihood of wafer warpage during thecuring process.

FIGS. 3A-3C are cross-sectional and top plan views of an assembly 300comprising a wafer 301 having a plurality of stacks 303 (identifiedindividually by reference numbers 303 a-h) of semiconductor dies thereonat various stages of processing in accordance with another embodiment ofthe present technology. FIG. 3A illustrates an assembly 300 that can besubstantially similar to the assembly 100 at the point of processingshown in FIG. 1D. For example, the stacks 303 are disposed in an arrayacross the upper surface 305 of the wafer 301. The wafer 301 is disposedover and supported by a support substrate 307. In the illustratedembodiment, each individual stack 303 includes four semiconductor dies309 a-d stacked vertically on top of one another and the foursemiconductor dies 309 a-d are stacked over a logic circuit 311 formedin or on the wafer 301.

Each stack 303 defines a substantially rectangular geometric prismhaving side surfaces 315 a and 315 c, a lower surface 317 adjacent tothe logic circuit 311, and an upper surface 319 opposite the lowersurface 317. Adjacent stacks 303 are laterally separated by a pluralityof gaps 321 a-g (collectively gaps 321). The assembly 300 also includesa first sealing material 323 in a first subset of the gaps 321 a-gbetween adjacent stacks 303, but not in a second subset of the gaps 321a-g. In the illustrated embodiment, the first sealing material 323 fillsa first subset of the gaps 321 including gaps 321 a, 321 c, 321 e, and321 g. The first sealing material 323 is absent from a second subset ofthe gaps 321 including gaps 321 b, 321 d, and 321 f.

FIG. 3B is a cross-sectional view of the assembly 300 after portions ofthe first sealing material 323 have been removed from the first subsetof gaps 321. In the illustrated embodiment, a wafer saw can be used toremove portions of the first sealing material 323 from the gaps 321 a,321 c, 321 e, and 321 g into which it has been dispensed. In someembodiments, at least 25% of the first sealing material 323 can beremoved from the select gaps 321. In some embodiments, at least 50%, atleast 75%, or more of the first sealing material 323 can be removed fromthe select gaps 321 using a wafer saw or other technique.

FIG. 3C is a cross-sectional view of the assembly 300 after a secondsealing material 331 is deposited over the stacks 303 and into each ofthe gaps 321, similar to the process described above with respect toFIG. 1E. The second sealing material 331 fills both the first subset ofgaps 321 a, 321 c, 321 e, and 321 g in which there is no first sealingmaterial 323 present and the second subset of gaps 321 b, 321 d, and 321f which are partially filled with the first sealing material 323. Theassembly 300 can then be annealed to cure the first and second sealingmaterials 323 and 331.

FIG. 3D is a cross-sectional view of the assembly 300 after an upperportion the second sealing material 331 shown in FIG. 3C is partiallyremoved by backgrinding and planarization until it is coplanar with thestacks 303, similar to the process described above with respect to FIG.1F. Following backgrinding and planarization, the support substrate 307can be removed, the wafer 301 attached to tape, and the individualstacks 303 singulated using a wafer saw or other technique.

FIG. 4A is a top plan view of a portion of the assembly 300 of FIG. 3D.Four individual stacks 303 i-l are arranged in an array over the wafer301. The first sealing material 323 is in the gap 321 h that separatesthe left stacks 303 i and 303 j from the right stacks 303 k and 303 l.The second sealing material 331 is also in the gap 321 h on top of thefirst sealing material 323 in addition to being in the gap 321 iseparating the upper stacks 303 i and 303 k from the lower stacks 303 jand 303 l. The second sealing material 331 further surrounds theremaining sides of the stacks 303 i-l. The assembly 300 is diced tosingulate the stacks 303 i-l, including dicing along the gaps 321 h and321 i. FIG. 4B is a cross-sectional view of the portion of the assembly300 of FIG. 4A taken along line B-B after singulating the stacks 303,and FIG. 4C is a cross-sectional view of the portion of the assembly 300of FIG. 4A taken along line C-C after singulating the stacks 303.Referring to FIGS. 4B and 4C together, after singulation each of thestacks 303 i-l has four sides. Of the four sides, the second sealingmaterial is disposed completely over three of the four sides. Withrespect to the remaining side of each stack 303, it is partially coveredby the first sealing material 323 and partially covered by the secondsealing material 331. For example, the side of stack 303 i facing thegap 321 h has a lower portion 335 that is covered with the first sealingmaterial 323 and an upper portion 337 that is covered with the secondsealing material 331. The first sealing material 323 also fills in theareas between individual semiconductor dies 309 of the individual stacks303.

FIG. 5 is a cross-sectional view of a singulated stack 503 of diesintegrated into a larger device assembly 500. As illustrated, the stack503 includes multiple memory dies 509 a-d disposed over an input/outputdie 511. The stack 503 is mounted over an interposer substrate 551, forexample via micropillars 553, with an adjacent system-on-chip 555 spacedlaterally adjacent to the stack 503 and also mounted over the interposersubstrate 551. The interposer substrate 551, in turn, is mounted to apackage substrate 557 via solder balls 559. The package substrate 557includes a plurality of package solder balls 561 for electrical andmechanical connection between the package substrate 557 and anothersystem. For example, the assembly 500 can be mounted to a PCB or othersurface. A third sealing material 563, such as an encapsulant, isdisposed over and seals the stack 503 as well as the system-on-chip 555.

Any one of the stacks of dies described above with reference to FIGS.1-5 can be incorporated into any of a myriad of larger and/or morecomplex systems, a representative example of which is system 600 shownschematically in FIG. 6. The system 600 can include a stackedsemiconductor die assembly 610, a power source 620, a driver 630, aprocessor 640, and/or other subsystems or components 650. The stackedsemiconductor die assembly 610 can include features generally similar tothose of the stacked die assemblies described above, and can thereforeinclude one or more sides at least partially covered with a firstsealing material and other sides covered with a second sealing material.The resulting system 600 can perform any of a wide variety of functions,such as memory storage, data processing, and/or other suitablefunctions. Accordingly, representative systems 600 can include, withoutlimitation, hand-held devices (e.g., mobile phones, tablets, digitalreaders, and digital audio players), computers, and appliances.Components of the system 600 may be housed in a single unit ordistributed over multiple, interconnected units (e.g., through acommunications network). The components of the system 600 can alsoinclude remote devices and any of a wide variety of computer-readablemedia.

From the foregoing, it will be appreciated that specific embodiments ofthe invention have been described herein for purposes of illustration,but that various modifications may be made without deviating from thedisclosure. Certain aspects of the new technology described in thecontext of particular embodiments may also be combined or eliminated inother embodiments. Moreover, although advantages associated with certainembodiments of the new technology have been described in the context ofthose embodiments, other embodiments may also exhibit such advantagesand not all embodiments need necessarily exhibit such advantages to fallwithin the scope of the technology. Accordingly, the disclosure andassociated technology can encompass other embodiments not expresslyshown or described herein.

I/We claim:
 1. A semiconductor device comprising: a first chip includinga first plurality of side surfaces; a second chip including a secondplurality of side surfaces, the second chip being stacked with the firstchip; a first sealing material provided in direct contact with a firstone of the first plurality of side surfaces of the first chip andfilling a space between the first chip and the second chip; and a secondsealing material provided in direct contact with a remaining one or onesof the first plurality of side surfaces of the first chip and in directcontact with the plurality of side surfaces of the second chip, thesecond sealing material being different from the first sealing material.2. The semiconductor device according to claim 1 wherein the firstsealing material has a first filler containing ratio and the secondsealing material has a second filler containing ratio that is largerthan the first filler containing ratio.
 3. The semiconductor deviceaccording to claim 1 wherein the second sealing material does not occupythe space between the first chip and the second chip and is in contactwith the first sealing material.
 4. The semiconductor device accordingto claim 1, further comprising an interface chip stacked with the firstchip, and wherein each of the first and the second chips comprises amemory chip.
 5. The semiconductor device according to claim 4, furthercomprising a third sealing material provided in contact with each of theside surfaces of the interface chip and with the first and the secondsealing materials.
 6. A semiconductor device comprising: a stack of aplurality of semiconductor dies, each of the plurality of semiconductordies having a plurality of side surfaces; a first sealing materialdisposed directly on one of the plurality of side surfaces of a firstone of the plurality of semiconductor dies and extending between eachadjacent pair of dies of the stack; and a second sealing materialdisposed directly on another one of the plurality of side surfaces ofthe first one of the plurality of semiconductor dies, the second sealingmaterial having a lower thermal cure shrinkage coefficient than thefirst sealing material.
 7. The semiconductor device of claim 6 whereinthe first sealing material has a lower filler containing ratio than thesecond sealing material.
 8. The semiconductor device of claim 6 whereinthe stack of the plurality of semiconductor dies includes an interfacechip and a memory chip.
 9. The semiconductor device of claim 6, whereinthe first sealing material comprises a capillary under fill (CUF)material and the second sealing material comprises a mold resinmaterial.